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general description the DS3501 is a 7-bit, nonvolatile (nv) digital poten- tiometer featuring an output voltage range of up to 15.5v. programming is accomplished by an i 2 c-compatible interface, which can operate at speeds of up to 400khz. external voltages are applied at the rl and rh inputs to define the lowest and highest potentiometer outputs. the DS3501 contains an on-chip temperature sensor and associated analog-to-digital converter (adc). the adc output addresses a 36-word nv lookup table (lut). the lut output can drive the pot directly or be added to an nv initial-value register (ivr) to drive the pot. this flexible lut-based architecture allows the DS3501 to provide a temperature-compensated poten- tiometer output with arbitrary slope. applications tft-lcd v com calibration linear and nonlinear compensation instrumentation and industrial controls mechanical pot replacement optical transceivers features ? 128 wiper tap points ? full-scale resistance: 10k ? on-chip temperature sensor and adc ? 36-byte lookup table (lut) ? i 2 c-compatible serial interface ? address pins allow up to four DS3501s to share the same i 2 c bus ? digital operating voltage: 2.7v to 5.5v ? analog operating voltage: 4.5v to 15.5v ? operating temperature: -40c to +100c ? pin and software compatible with isl95311 (default mode) ? 10-pin sop package DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table ______________________________________________ maxim integrated products 1 rev 0; 1/07 + denotes a lead-free package. t&r denotes tape-and-reel. ordering information part temp range pin-package DS3501u+ -40? to +100? 10 ?op DS3501u+t&r -40? to +100? 10 ?op volatile wiper register nv ivr 36-byte lut nv memory control circuitry and address decode temp sensor and adc a1 a0 sda scl decoder level shifter 127 126 125 2 1 0 rh rl rw DS3501 functional diagram pin configuration and typical operating circuit appear at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +100?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc relative to gnd ...............-0.5v to +6.0v voltage range on v+ relative to gnd ..................-0.5v to +17v voltage range on sda, scl, a0, a1 relative to gnd..........-0.5v to (v cc + 0.5v), not to exceed 6.0v voltage range on rh, rl, rw...................................-0.5v to v+ voltage range across rh and rl pins .....................-0.5v to v+ operating temperature range .........................-40? to +100? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature .......................................see ipc/jedec j-std-020 specification maximum rw current ...........................................................1ma parameter symbol conditions min typ max units supply voltage v cc (note 1) +2.7 +5.5 v v+ voltage v+ v+ > v cc +4.5 +15.5 v input logic 1 (scl, sda, a0, a1) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (scl, sda, a0, a1) v il -0.3 0.3 x v cc v resistor inputs (rl, rw, rh) v res -0.3 v+ + 0.3 v wiper current i wiper 1ma dc electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +100?, unless otherwise noted.) parameter symbol conditions min typ max units i cc (note 2) 2 ma v cc supply current i cc2 (note 3) 250 350 ? standby supply current i stby (note 4) 40 60 ? v+ bias current i v+ +1 ? inp ut leakag e ( s d a, s c l, a0, a1) i l -1 +1 ? low-level output voltage (sda) v ol 3ma sink current 0.0 0.4 v i/o capacitance c i/o 510pf power-up recall voltage v por (note 5) 1.6 2.6 v power-up memory recall delay t d (note 6) 5 ms wiper resistance r w v+ = 15.0v 5000 e nd - to- e nd resi stance ( rh to rl) r total 10 k r total tolerance t a = +25? -20 +20 % r total temp co. (note 7) ?00 ppm ch, cl, cw capacitance c pot 10 pf
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table _____________________________________________________________________ 3 analog voltage monitoring characteristics (v cc = +2.7v to +5.5v, t a = -40? to +100?, unless otherwise noted.) parameter symbol conditions min typ max units supply resolution lsb full-scale voltage of 6.5536v 25.6 mv input/supply accuracy a cc at factory setting 0.25 1 % fs (full scale) input supply offset v os (note 7) 0 5 lsb update rate (temperature and supply conversion time) t frame 16 ms temperature sensor characteristics (v cc = +2.7v to +5.5v, t a = -40? to +100?, unless otherwise noted.) parameter symbol conditions min typ max units temperature error ? ? update rate (temperature and supply conversion time) t frame 16 ms voltage-divider characteristics (v cc = +2.7v to +5.5v, t a = -40? to +100?, unless otherwise noted.) parameter symbol conditions min typ max units integral nonlinearity inl (note 8) -1 +1 lsb differential nonlinearity dnl (note 9) -0.5 +0.5 lsb zero-scale error zs error v+ = 4.5v (note 10) 0 0.5 2 lsb full-scale error fs error v+ = 4.5v (note 11) -2 -0.003 0 lsb ratiometric temp coefficient tcv wr set to 40h ? ppm/? i 2 c ac electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +100?, timing referenced to v il(max) and v ih(min) . see figure 3.) parameter symbol conditions min typ max units scl clock frequency f scl (note 12) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ?
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table 4 _____________________________________________________________________ nonvolatile memory characteristics (v cc = +2.7v to +5.5v) parameter symbol conditions min typ max units t a = +70? 50,000 eeprom write cycles t a = +25? 200,000 writes note 1: all voltages are referenced to ground. currents entering the ic are specified positive and currents exiting the ic are nega- tive. note 2: i cc is specified with the following conditions: scl = 400khz; sda pulled up; and rl, rw, rh floating. note 3: i cc is specified with the following conditions: scl, sda pulled up; rl, rw, rh floating; and temperature sensor on. note 4: i stby is specified with sda = scl = v cc = 5.5v, resistor pins floating, and cr2 bit 0 = logic-high. note 5: this is the minimum v cc voltage that causes nv memory to be recalled. note 6: this is the time from v cc > v por until initial memory recall is complete. note 7: guaranteed by design. note 8: integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resis- tor setting. expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. inl = [v(rw) i - (v(rw) 0 ] / lsb(ideal) - i, for i = 0...127. note 9: differential nonlinearity is the deviation of the step-size change between two lsb settings from the expected step size. the expected lsb step size is the slope of the straight line from measured minimum position to measured maximum position. dnl = [v(rw) i+1 - (v(rw) i ] / lsb(ideal) - 1, for i = 0...126. note 10: zs error = code 0 wiper voltage divided by one lsb(ideal). note 11: fs error = (code 127 wiper voltage - v+) divided by one lsb (ideal). note 12: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c standard mode timing. note 13: cb?otal capacitance of one bus line in picofarads. note 14: eeprom write time begins after a stop condition occurs. note 15: pulses narrower than max are suppressed. i 2 c ac electrical characteristics (continued) (v cc = +2.7v to +5.5v, t a = -40? to +100?, timing referenced to v il(max) and v ih(min) . see figure 3.) parameter symbol conditions min typ max units data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 13) 20 + 0.1c b 300 ns sda and scl fall time t f (note 13) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 13) 400 pf eeprom write time t w (note 14) 10 20 ms pulse-width suppression time at sda and scl inputs t in (note 15) 50 ns a0, a1 setup time t su:a before start 0.6 ? a0, a1 hold time t hd:a after stop 0.6 ? sda and scl input buffer hysteresis 0.05 x v cc v
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table _____________________________________________________________________ 5 typical operating characteristics (t a = +25?, unless otherwise noted.) typical operating characteristics (t a = +25?, unless otherwise noted.) 20 70 120 170 220 -40 0 -20 20 40 60 80 100 supply current vs. temperature DS3501 toc01 temperature ( c) supply current ( a) lut mode default mode v+ = 15.5v, v cc = 5v sda = scl = v cc ; rh, rl, rw are floating 20 70 170 120 220 supply current vs. supply voltage DS3501 toc02 supply voltage (v) supply current ( a) 2.7 4.1 5.5 lut mode default mode v+ = 15.5v sda = scl = v cc ; rl, rh, rw are floating 30 32 31 34 33 35 36 -40 20 40 -20 0 60 80 100 standby supply current vs. temperature DS3501 toc03 temperature ( c) standby supply current ( a) lut mode default mode v+ = 15.5v, v cc = 5v sda = scl = v cc ; rh, rl, rw are floating -0.75 -0.50 -0.25 0 0.25 0.50 0.75 032 16 48 64 80 96 112 integral nonlinearity vs. potentiometer setting DS3501 toc04 potentiometer setting (dec) integral nonlinearity (lsb) -0.75 -0.50 -0.25 0 0.25 0.50 0.75 032 16 48 64 80 96 112 differential nonlinearity vs. potentiometer setting DS3501 toc05 potentiometer setting (dec) differential nonlinearity (lsb) pin description name pin description sda 1 i 2 c serial data. input/output for i 2 c data. gnd 2 ground terminal v cc 3 supply voltage terminal a1, a0 4, 5 address select inputs. determines i 2 c slave address. slave address is 01010a 1 a 0 x. (see the slave address byte and address pins section for details). rh 6 high terminal of potentiometer rw 7 wiper terminal of potentiometer rl 8 low terminal of potentiometer v+ 9 wiper bias voltage scl 10 i 2 c serial clock. input for i 2 c clock.
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table 6 _____________________________________________________________________ i 2 c interface wiper register/ initial value register (wr/ivr) 00h v cc sda a0 a1 control logic/ registers rh rl v+ pos 7fh pos 00h gnd scl see bit rw DS3501 default mode block diagram (update mode bit = 0) i 2 c interface lut address register control logic/ registers adc v cc sda a0 a1 gnd scl temp sensor v cc voltage temp 0ch v cc (v) 0eh data control rh rl v+ pos 7fh pos 00h rw (lutar) 08h 36 byte lookup table (lut) 80h-a3h wiper register (wr) 09h* initial value register (ivr) 00h* on power-up only when in lut-adder mode ivr lutval or lutval+ivr lutval *note that when in lut or lut adder mode, wr is accessed through 09h (unlike default mode) while ivr remains at 00h. DS3501 lut and lut adder mode block diagram (update mode bit = 1) block diagrams
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table _____________________________________________________________________ 7 detailed description the DS3501 operates in one of three operating modes: default mode, lut mode, or lut adder mode. in default mode, the DS3501 is pin and software compati- ble with the isl95311. the potentiometer? wiper posi- tion is controlled by the wiper register (wr) and the nv initial value register (ivr) via the i 2 c interface. in lut mode and lut adder mode, the potentiometer? wiper position is calculated/controlled as a function of the current temperature measured by the DS3501? internal temperature sensor. the difference between the two lut modes is the way the potentiometer wiper position is calculated. a detailed description of the three modes as well as additional features of the DS3501 follow below. digital potentiometer output the potentiometer consists of 127 resistors in series connected between the rh and rl pins. between each resistance and at the two end points, rh and rl, solid- state switches enable rw to be connected within the resistive network. the wiper position and the output on rw are decoded based on the value in wr. if rh, rl, and rw are externally connected in a voltage-divider configuration, then the voltage on rw can be easily calculated using the following equation: where wr is the wiper position in decimal (0?27). temperature conversion and supply voltage monitoring temperature conversion the DS3501 features an internal 8-bit temperature sen- sor that is capable of driving the lut and providing a measurement of the ambient temperature over i 2 c by reading address 0ch. the sensor is functional over the entire operating temperature range and is in signed two? complement format with a resolution of 1?/bit. see below for the temperature sensor? bit weights. to calculate the temperature, treat the two? comple- ment binary value as an unsigned binary number, then convert it to decimal. if the result is greater than or equal to 128, subtract 256 from the result. supply voltage monitoring the DS3501 also features an internal 8-bit supply volt- age (v cc ) monitor. a value of the supply voltage mea- surement can be read over i 2 c at the address 0eh. to calculate the supply voltage, simply convert the hexadecimal result into decimal and then multiply it by the lsb as shown in the analog voltage monitoring characteristics electrical table. mode selection the DS3501 mode of operation is determined by two bits located in control register 1 (cr1), which is non- volatile. in particular, the mode is determined by the update mode bit (cr1.0) and the adder mode bit (cr1.1). table 1 illustrates how the two control bits are used to select the operating mode. when shipped from the factory, the DS3501 is programmed with the cr1.0 bit = 0, hence configuring the DS3501 in default mode. default mode default mode of the DS3501 is the simplest mode of the three. as shown in the default mode block diagram, the potentiometer is controlled by the wiper register/ initial value register (wr/ivr). upon power-up of the DS3501, the value stored in the nv initial value register (ivr) is recalled into the volatile wiper register (wr). the wiper can then be changed any time after by writing the desired value to the wr/ivr register. the wr/ivr register is located at memory address 00h and is implemented as eeprom shad- owed sram. this register can be visualized as an sram byte (the wr portion) in parallel with a eeprom byte (the ivr portion). the operation of the register is controlled by the shadow eeprom ( see ) bit, cr0.7. when the see bit = 0 (default), data written to memory address 00h by i 2 c actually gets stored in both sram (wr) and eeprom (ivr). conversely, when see = 1, only the sram (wr) is written to the new value. the eeprom byte (ivr) continues to store the last value written to it when see was 0. reading memory address 00h reads the value stored in wr. as shown in the default mode memory map (see table 2), the see bit is volatile and its power-up default state is 0. vv wr vv rw rl rh rl =+ ? () 127 s2 6 2 5 2 4 2 3 2 2 2 1 2 0 update mode bit (cr1.0) adder mode bit (cr1.1) mode 0 x default mode (default) 1 0 lut mode 1 1 lut adder mode table 1. DS3501 operating modes
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table 8 _____________________________________________________________________ lut mode lut mode is selected by setting the update mode bit (cr1.0) to 1 and the adder mode bit (cr1.1) to 0. an overview of the DS3501 in this mode is illustrated in the lut mode and lut adder mode block diagram. also, the memory map for lut mode and lut adder mode is shown in table 3. the major difference between the two lut modes is whether or not the value in the ivr is added to the values stored in the lookup table. the dashed line/arrow shown in the block diagram is not active in lut mode. when in lut mode, on power-up the ivr value is recalled into the wr register. this value will remain there until completion of the first temperature conver- sion following power-up. the temperature is measured every t frame . the temperature value is used to calcu- late an index that points to the corresponding value in the lookup table. this index is referred to as the lut address register (lutar). the value stored in the lut at the location pointed to by lutar is called lutval. the wiper register is then automatically loaded with lutval. the process then repeats itself, continuously updating the wiper setting in a closed-loop fashion. in this mode the 36-byte lut is populated with wiper settings for each four-degree temperature window. valid wiper settings are 00h to 7fh. the memory map in table 3 shows the memory address of the lut as well as the corresponding temperature range for each byte in the lut. also, the lut features one-degree hystere- sis to prevent chattering if the measured temperature register name address (hex) volatile/nonvolatile factory/power-up default wr/ivr wiper register/initial value 00h* nv (shadowed) 40h cr0 control register 0 02h v 00h cr1 control register 1 03h nv (shadowed) 00h cr2 control register 2 0ah v 00h table 2. default mode memory map * in default mode, both wr and ivr are accessed through memory location 00h. refer to the default mode section for additional inf ormation. register name address (hex) volatile/nonvolatile factory/power-up default ivr initial value register 00h* nv (shadowed) 40h cr0 control register 0 02h v 00h cr1 control register 1 03h nv (shadowed) 00h lutar lut address register 08h v n/a wr wiper register 09h* v n/a cr2 control register 2 0ah v 00h temp temperature value 0ch v (read-only) n/a vcc v cc voltage value 0eh v (read-only) n/a lut0 wiper value for t -37? 80h nv 00h lut1 wiper value for -36? to -33? 81h nv 00h lut2 wiper value for -32? to -29? 82h nv 00h lut33 wiper value for +92? to +95? a1h nv 00h lut34 wiper value for +96? to +99? a2h nv 00h lut35 wiper value for t 100? a3h nv 00h table 3. lut mode and lut adder mode memory map * in lut mode and lut adder mode, the wr is accessed through memory address 09h, while ivr remains at memory address 00h.
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table _____________________________________________________________________ 9 falls on the boundary between two windows. as the temperature increases, the lut changes on even tem- perature values (see figure 1). conversely, the lut changes on odd temperature values when the tempera- ture is decreasing. lut adder mode lut adder mode is selected by setting the update mode bit (cr1.0) to 1 and the adder mode bit (cr1.1) to 1. this mode operates similar to lut mode with one major difference (see the lut mode and lut adder mode block diagram). the wiper register is loaded with the sum of lutval and ivr. furthermore, in this mode, the values programmed into the lut are signed two? complement. this allows convenient positive or negative offsetting of the nominal ivr value. memory location lut20 lut19 lut18 lut17 lut16 24 28 32 36 40 44 increasing temperature temperature ( c) 1 c hysteresis window decreasing temperature figure 1. lut hysteresis control register 1 (cr1) factory default 00h memory type shadowed nonvolatile 03h reserved reserved reserved reserved reserved reserved adder mode update mode bit7 bit0 bit7:2 reserved bit1 adder mode: this bit is valid only if the update mode bit = 1. 0 = sets the DS3501 to lut mode. 1 = sets the DS3501 to lut adder mode. bit0 update mode: 0 = sets the DS3501 to default mode. in this mode the DS3501 is compatible with the isl95311 (default). 1 = sets the DS3501 to one of the two lut-based modes depending on the adder mode bit. control register 0 (cr0) power-up default 00h memory type volatile 02h see reserved reserved reserved reserved reserved reserved reserved bit7 bit0 bit7 see : controls functionality of shadowed nv registers (such as the wr/ivr register). 0 = data written to shadowed nv memory is stored in both sram and eeprom (default). 1 = data written to shadowed nv memory is stored only in sram. bit6:0 reserved DS3501 control registers the DS3501 contains three control registers (cr0, cr1, and cr2) used to configure and control modes and features.
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table 10 ____________________________________________________________________ standby mode and i cc the DS3501 has three specified levels of supply cur- rent. active current during i 2 c communications while in the lut-driven mode is specified as i cc , and is the ?orst-case?supply current. active current without i 2 c communications while in the lut driven mode is speci- fied as the supply current: i cc2 . sda and scl are held statically in the high-logic level while the DS3501 con- tinues to function in lut-driven mode. the third level is specified as standby mode, i stby . this is the lowest possible current consumption mode. standby mode is enabled with cr2.0 = 1. all internal operations are halted including internal temperature sensor results. consequently, wr? position will not change, and will remain in the last state that was loaded into wr. i 2 c will, however, continue to function, and once cr2.0 = 0, the DS3501 will resume normal operation after the first temperature conversion cycle is complete (t frame ). slave address byte and address pins the slave address byte consists of a 7-bit slave address plus a r/ w bit (see figure 2). the DS3501? slave address is determined by the state of the a0 and a1 address pins. these pins allow up to four devices to reside on the same i 2 c bus. address pins tied to gnd result in a 0 in the corresponding bit position in the slave address. conversely, address pins tied to v cc result in a 1 in the corresponding bit positions. for example, the DS3501? slave address byte is 50h when a0 and a1 pins are grounded. i 2 c communication is described in detail in the i 2 c serial interface description section. i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. (see figure 3 and i 2 c ac electrical characteristics table for additional information.) master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. control register 2 (cr2) power-up default 00h memory type volatile 0ah reserved reserved reserved reserved reserved ten aen standby bit7 bit0 bit7:3 reserved bit2 ten: temperature update enable bar. this bit is valid only in lut mode and lut adder mode. 0 = normal lut operation. the wr is automatically loaded with lutval+ivr or lutval following each temperature conversion. 1 = places the potentiometer in manual mode allowing wr (09h) to be written using i 2 c. bit1 aen: address update enable bar. this bit is valid only in lut mode and lut adder mode. 0 = normal lut operation. lutar (08h) is calculated following each temperature conversion that points to the corresponding location in the lut. 1 = disables automatic updates of lutar. this allow the user to directly write to the lutar register in order to exercise lut values and functionality. bit0 standby: 0 = normal operating mode. 1 = standby mode. places the DS3501 in a low-power consumption state specified by i stby . the i 2 c interface is still active in this state. 0 1 1 0 r/w a0 a1 0 msb lsb slave address* *the slave address is determined by address pins a0, a1. figure 2. DS3501 slave address byte
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table ____________________________________________________________________ 11 slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a spe- cific memory address to begin a data transfer. a repeat- ed start condition is issued identically to a normal start condition. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements. data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a 0 during the 9th bit. a device performs a nack by trans- mitting a 1 during the 9th bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or indicates that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgment is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is reference to v il(max) and v ih(min) . start figure 3. i 2 c timing diagram
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table 12 ____________________________________________________________________ minate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately fol- lowing a start condition. the slave address byte con- tains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the slave address byte of the DS3501 is shown in figure 2. when the r/ w bit is 0 (such as in 50h), the master is indicating it will write data to the slave. if r/ w = 1 (51h in this case), the master is indicating it wants to read from the slave. if an incorrect slave address is written, the DS3501 assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must gen- erate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgment during all byte write operations. when writing to the DS3501, the potentiometer will adjust to the new setting once it has acknowledged the new data that is being written, and the eeprom (if see = 0) will be written following the stop condition at the end of the write command. to change the setting without changing the eeprom, terminate the write with a repeat- ed start condition before the next stop condition occurs. using a repeated start condition prevents the t w delay required for the eeprom write cycle to finish. writing multiple bytes to a slave: to write multiple bytes to a slave in one transaction, the master gener- ates a start condition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. the DS3501 is capable of writing 1 to 8 bytes (1 page or row) in a single write transaction. this is internally con- trolled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). the first page begins at address 00h and subsequent pages begin at multiples of 8 (08h, 10h, 18h, etc). attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrap- ping around to the beginning of the present row. to prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or eeprom-write time to elapse. then the master can generate a new start condition and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time a eeprom byte is written, the DS3501 requires the eeprom write time (t w ) after the stop condition to write the contents of the byte to eeprom. during the eeprom write time, the device will not acknowledge its slave address because it is busy. it is possible to take advantage of this phenomenon by repeatedly addressing the DS3501, which allows communication to continue as soon as the DS3501 is ready. the alternative to acknowledge polling is to wait for a maximum period of t w to elapse before attempting to access the device. eeprom write cycles: the DS3501? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature (hot) as well as at room tem- perature. writing to shadowed eeprom with see = 1 does not count as a eeprom write. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read opera- tion occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the master gen- erates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condi- tion, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. see figure 4 for a read example using the repeated start condition to specify the starting memory location.
DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table ____________________________________________________________________ 13 reading multiple bytes from a slave: the read opera- tion can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and generates a stop condition. applications information power-supply decoupling to achieve the best results when using the DS3501, decouple both the power-supply pin and the wiper-bias voltage pin with a 0.01? or 0.1? capacitor. use a high-quality ceramic surface-mount capacitor if possi- ble. surface-mount components minimize lead induc- tance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. sda and scl pullup resistors sda is an i/o with an open-collector output that requires a pullup resistor to realize high-logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics are within specification. a typ- ical value for the pullup resistors is 4.7k . chip information transistor count: 22,400 substrate connected to ground slave address* start start 0 1 0 1 0 a1 a0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 data stop single-byte write -write lutar register to 00h single-byte write set to lut mode single-byte read -read cr0 register two-byte write - write 80h and 81h to 00h start repeated start 51h master nack stop 0 1010000 00000 010 02h 01010 001 0 1010000 00001 000 50h 08h stop start 0 1010000 00000 011 50h cr1 (03h) stop data 01h example i 2 c transactions (when a0 and a1 are connected to gnd). typical i 2 c write transaction *the slave address is determined by address pins a0 and a1. 00000 000 0 000 0 0 01 50h a) c) b) d) slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack start 0 1010000 10000 000 50h 80h stop 00h 0 000 0 0 00 slave ack slave ack slave ack 00h 0 000 0 0 00 slave ack two-byte read - read 80h and 81h e) start 0 1010000 10000 000 50h 80h stop slave ack slave ack slave ack master ack 51h 0 101 0 0 01 data data master ack lut 1 lut 0 repeated start figure 4. i 2 c communication examples
v cc 2.7v gnd rl rw v+ rh scl i 2 c c lcd v com r1 g1 b1 gate 1 gate 2 gate 3 c stor tft a1 a0 15.0v sda DS3501 typical operating circuit 10 9 8 7 6 1 2 3 4 5 scl v+ rl rw a1 v cc gnd sda top view rh a0 DS3501 pin configuration package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . DS3501 high-voltage, nv, i 2 c pot with temp sensor and lookup table maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. heaney

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